The performance of an on-chip interconnect, such as an on-chip transmission line, is a significant factor in affecting overall chip performance. On-chip transmission lines are often modeled before production begins in an effort to lessen design time. Due to the significance of an on-chip transmission line to overall chip performance, accurate models of the on-chip transmission line are necessary when evaluating high performance designs. Any error that is present in the model of the transmission line may result in an inaccurate estimate of the characteristic impedance and/or attenuation associated with the transmission line in the chip. Chips that are produced based on faulty modeling may not perform in the manner required by the design specification, and as such represent an inefficient use of time, effort, and capital.
A common type of on-chip transmission line is a coplanar waveguide. A traditional coplanar waveguide comprises a signal line flanked by two ground lines. All three lines, e.g., the signal line and the two ground lines, are formed in a common wiring level of a semiconductor structure and thus are coplanar in a substantially horizontal plane.
Traditional on chip coplanar waveguides are difficult to model because asymmetry of the semiconductor structure in the vicinity of the coplanar waveguide results in an asymmetric electrical field that is difficult to model. Difficulties in modeling traditional coplanar waveguides are compounded when the electrical field intersects air, e.g., above the coplanar waveguide, or silicon substrate, e.g., below the coplanar waveguide. This is because there are no highly accurate models for the effects of air and/or substrate coupling. As a result, rather than using modeling, most designers rely on hardware measurements of fabricated prototypes to verify chip designs, which slows down the design cycle and the time to market for the product.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.